1. Field of the Invention
This invention relates to a semiconductor package having semiconductor devices packaged onto a substrate. More particularly, the invention relates to a small and high-performance semiconductor package capable of high-density packaging or a so-called “CSP (chip size package)”. The invention further relates to a method of producing such a semiconductor package easily, and at a high yield, at a wafer level.
2. Description of Related Art
To cope with the higher performance and the reduction in size, so-called, “down sizing”, of electronic appliances, various types of semiconductor packages have been proposed, in recent years, which combine semiconductor devices such as IC chips, LSI chips, etc, or semiconductor devices having semiconductor chips mounted onto a substrate. To accomplish high-density packaging in such a semiconductor package, various research institutes and companies have proposed models of three-dimensional packaging. Though a method that superposes semiconductor chips with one another and connects them through bonding wires has been proposed, the most promising method may be the one that the superposed semiconductor chips are bonded with one another, through flip chips (FC) and an under-fill material is filled between the chips.
Recently, a down-sized semiconductor package having no FC has been proposed. As shown in FIG. 1, for example, a stacked semiconductor device 114 fabricated by stacking a plurality of wafers (semiconductor chips) 105 on a pattern film 104 through an insulating adhesive 006 has been proposed (see, Japanese Unexamined Patent Publication (Kokai) No. 2000-252411). In this stacked semiconductor device 114, a longitudinal wiring pattern 116 is formed on outer and inner peripheries of the stacked body of the wafers 105 and external connection terminals 111 are arranged on the lower surface of the pattern film 105 through an external connection pattern 103. In the case of this stacked semiconductor device, however, stacking of the wafers, dicing, silicon etching and application of the insulating adhesive must be repeatedly carried out to form a stacked body having a plurality and desired number of stages of wafers, and the production steps are extremely complicated. Another problem is that the formation step of the longitudinal wiring pattern must be included separately.
A semiconductor device 161 fabricated by first producing semiconductor chips 162 having protrusive electrodes 164 on opposite surfaces thereof and stacking a plurality (six, in the drawing) of semiconductor chips 162 in such a fashion as to butt against one another as shown in FIG. 2 has also been proposed (see, Japanese Unexamined Patent Publication (Kokai) No. 2001-94039). Each semiconductor chip 162 has an insulating layer 172 on each surface thereof and a through-hole 166 formed between its opposite surfaces. An insulating film 168 and a conductor member 170 are serially formed inside the through-hole 166. However, because this semiconductor device employs the method that serially stacks the semiconductor chips, it has the drawback that the production yield is low. Further, the transfer step for the insulating layer, using a mold, is complicated.